1. Field of the Invention
The present invention relates to a static semiconductor memory device and a method of controlling the same and, more particularly, to a static semiconductor memory device having memory cells each formed from four transistors and a method of controlling the same.
2. Description of the Related Art
A conventional example of a static semiconductor memory device having memory cells each formed from four transistors is an SRAM (Static Random Access Memory) having 4Tr (transistor) memory cells (the SRAM will be referred to as a 4Tr SRAM hereinafter). FIG. 6 is a view showing the schematic arrangement of the memory cell array of the conventional 4Tr SRAM and a leakage current in read operation. The memory cell array shown in FIG. 6 is constituted by arraying static memory cells each formed from four transistors in a matrix.
As shown in FIG. 6, in the 4Tr SRAM, 256 memory cells (CELL0, CELL1, . . . CELL255) M are connected to pairs of bit lines BL and XBL (for a 256-word structure). To select each memory cell M, word lines WL0, WL1, . . . , WL255 (to be referred to as word lines WL hereinafter) are connected in correspondence with the memory cells M. More specifically, a pair of bit lines BL and XBL arranged in correspondence with each column of the memory cell array and the word line WL arranged in correspondence with each row of the memory cell array are connected to each memory cell M.
The memory cell M is constituted by a pair of transfer transistors T1 and T2 formed from p-MOS (Metal-Oxide Semiconductor) FETs (Field-Effect Transistors) and a pair of driver transistors T3 and T4 formed from n-MOSFETs. A sense amplifier SA is connected to the bit lines BL and XBL. The sense amplifier SA amplifies the potential difference between data read out from the memory cell M to the bit lines BL and XBL in read operation and reads out the data. At the time of accessing the memory cell M, the bit lines BL and XBL have a complementary relationship. When one bit line is at high level, the other is at low level. When the memory cell M is not accessed, both the bit lines are precharged to high level.
The gate and drain terminals of the above-described driver transistors T3 and T4 are cross-connected to form a flip-flop. The source terminals are connected to ground. A cross-connection point to the drain terminal of the driver transistor T3 is defined as a node A. A cross-connection point to the drain terminal of the driver transistor T4 is defined as a node B. The node A is connected to the bit line BL through the transfer transistor T1. The node B is connected to the bit line XBL through the transfer transistor T2. The word line WL is connected to the gate terminals of the transfer transistors T1 and T2.
In the memory cells M having the above-described arrangement, to hold data in the above-described node A or B, the word lines WL of the unselected memory cells M are set at high level. At this time, to prevent the potential (H or L level) of the node A or B from changing due to the first leakage current that leaks through the driver transistors T3 and T4, the second leakage current of the transfer transistors T1 and T2 connected to the bit lines BL and XBL is controlled. The relationship between the above-described first leakage current and the second leakage current will be described below.
Examples of the first leakage current from the node A or B of the memory cells M are a junction leakage, transistor leakage, and gate leakage. The second leakage current is generated by the gate voltages of the transfer transistors T1 and T2 and the potential difference between the bit lines BL and XBL and the nodes A and B of the memory cells M. Along with the recent development of micropatterning process, the above-described first leakage current tends to increase.
To hold data in the node A or B, the second leakage current must be set to be much larger than the first leakage current. To do this, the manufacturing process is adjusted in consideration of the mass productivity and the like such that the second leakage current has a magnitude about 100 times larger than that of the first leakage current of the memory cells M. In addition, to improve the data holding characteristics in the node A or B, the value of the voltage to be supplied to the word lines WL connected to unselected memory cells M is set to VDD-α (VDD: power supply voltage value, and α: value about 10% of the power supply voltage) to increase the second leakage current of the transfer transistors T1 and T2.
The operation of the above-described 4Tr SRAM will briefly be described next.
1. Read Operation
During the non-access period for the memory cells M, the bit lines BL and XBL are precharged to high level. When data is to be read out from the selected memory cell M during the access period, the word line WL connected to the selected memory cell M is set to low level. Accordingly, the transfer transistors T1 and T2 are turned on, and data held in the memory cell M is output to the bit lines BL and XBL. The word lines WL connected to the unselected memory cells M are kept at high level so that their transfer transistors T1 and T2 are kept OFF. In addition, the second leakage current flows to the transfer transistors T1 and T2 of the unselected memory cells M in accordance with the potential of the gate terminal at high level.
2. Write Operation
During the non-access period for the memory cells M, the bit lines BL and XBL are precharged to high level. When data is to be written in the selected memory cell M during the access period, the word line WL connected to the selected memory cell M is set to low level. Accordingly, the transfer transistors T1 and T2 are turned on to connect the bit lines BL and XBL to the memory cell M, and data is written by the bit lines BL and XBL. At this time, the second leakage current flows to the transfer transistors T1 and T2 of the unselected memory cells M in accordance with the potential of the gate terminal at high level, as in the read operation.
In the above-described conventional setting method, to hold data in the node A or B of the memory cells M, the potential of the word lines WL are set to VDD-α to increase the second leakage current of the transfer transistors T1 and T2. However, this setting method has the following three problems.
1. Degradation in Read Characteristics
As shown in FIG. 6, the 256 memory cells M (CELL0 to CELL255) are connected to the bit lines BL and XBL. In this case, “0”-data is written in the memory cell M (CELL0), and “1”-data is written in the memory cells M (CELL1 to CELL255). At this time, the node A of the memory cell M (CELL0) is at high level (H level), and the nodes A of the memory cells M (CELL11 to CELL255) are at low level (L level) (the node B is at a logic level opposite to that of the node A). If data should be read out from the memory cell M (CELL0) in this state, the following problems are posed. Note that the bit lines BL and XBL are precharged to high level at the start of access.
For example, the data (“0”-data) held in the memory cell M (CELL0) selected by setting the word line WL0 to low level is output to the bit lines BL and XBL as a read current Iread. A second leakage current Ileak flows to the transfer transistors T1 and T2 of the unselected memory cells M (CELL1 to CELL255) in accordance with the potential difference between the source and the drain or the gate potential.
A current IBL that flows to the bit line BL and a current IXBL that flows to the bit line XBL are given byIBL, IXBL=Iread+Ileak×255The current IBL flowing to the bit line BL is obtained. Since no discharge from the memory cell M (CELL0) occurs, the read current Iread flowing to the transfer transistor T1 is 0. In the memory cells M (CELL1 to CELL255), the leakage current Ileak flows from the bit lines BL to the 255 memory cells M through the transfer transistors T1. Hence, the current IBL is given byIBL=Ileak×255
Similarly, in the bit line XBL, all the nodes B of the memory cells M (CELL1 to CELL255) are at high level, For this reason, both the nodes B and the bit line XBL (precharged) on both sides of the transfer transistors T2 have the potential VDD-α. Hence, the leakage current Ileak flowing to the transfer transistors T2 is 0. In addition, since the bit line XBL is connected to ground through the node B and driver transistor T4 of the memory cell M (CELL0), the bit line XBL that has been precharged is discharged and the read current Iread flows. Hence, the current IXBL flowing to the bit line XBL is given byIXBL=Iread
Assume that, to improve the data holding characteristics of the memory cells M, the voltage VDD-α is controlled to be relatively low, and the second leakage current Ileak is set to a value much larger than that of the first leakage current. If Iread<Ileak×255, the bit line BL changes to low level earlier than the bit line XBL that should be changed to low level by the read operation. Hence, the read operation cannot be normally executed. Additionally, the sense amplifier SA must be activated after the amplitude of the bit lines BL and XBL sufficiently increases. If the potentials of the bit lines BL and XBL are unstable due to the second leakage current Ileak, as described above, the activation timing of the sense amplifier SA must be set with a margin. This impedes the speed of read operation increasing.
2. Increase in Probability of Write Error
FIG. 7 is a view showing the schematic arrangement of the memory cell array of the conventional 4Tr SRAM and a leakage current in write operation.
FIG. 7 shows a more simplified arrangement of the memory cell array of the 4Tr SRAM shown in FIG. 6. The same reference numerals as in FIG. 6 denote parts having the same functions in FIG. 7, and a description thereof will be omitted. Assume a case wherein “1”-data is written in an arbitrary memory cell M (CELLn) (n is one of 1 to 255) except the memory cell M (CELL0), as shown in FIG. 7. The memory cell M (CELL0) holds “0”-data. The node A is at high level, and the node B is at low level.
First, to write “1”-data in the memory cell M (CELLn), the bit line BL changes to low level. At this time, if a leakage current readily flows to the transfer transistor T1 of the memory cell M (CELL0) as an unselected cell, the second leakage current Ileak is generated from the node A of the memory cell M (CELL0) to the bit line BL. Accordingly, the potential (high level) of the node A of the memory cell M (CELL0) may decrease, and the data to be held may be lost.
3. Increase in Standby Current
During the non-access period (standby period) except the above-described access period (read and write operations), the signal level of the word lines WL connected to all the memory cells M is set to VDD-α, and both the bit lines BL and XBL are set to high level. At this time, since a leakage current flows to the transfer transistor T1 or T2, the data can be held. However, power consumption increases. That is, the standby current increases.